Modern electronic designs often include various cells such as some off-the-shelf configurable or non-configurable library cells, intellectual property (IP) cells, macro cells, etc. Each of these cells may be instantiated multiple times as instances in an electronic design so that when a designer desires or requires to make a change to this cell, the designer only needs to make the change once, and all the change will be automatically reflected in all the instances in the electronic design to save development efforts and to expedite the design cycles so as to shorten the time-to-market of the eventual products.
Conventional electronic design implementations include a top-down and a bottom-up approach. A top-down approach begins the implementation process at the top or highest hierarchy and proceeds to lower hierarchies until it reaches the lowest hierarchy to complete an IC design. With the top-down approach, the functional cells at a higher hierarchy may be brought into the layout canvas while each cell include its own pins, ports, or terminals (collectively pin for singular or pins for plural hereinafter). The details of these functional cells at lower hierarchies are not yet exposed and will be designed at respective lower hierarchies as the top-down approach migrates to lower hierarchies. As a result of the non-exposure or unavailability of lower hierarchies (e.g., the lower hierarchies have not yet been implemented), a circuit designer working on a higher hierarchy may need to estimate the size of each cell and guess or guesstimate the locations of pins or terminals for the cell. The estimated cell may be too big to waste invaluable space on silicon or may be too small to accommodate all the devices therein.
In addition to the manual efforts to create the location, identification, etc. for a pin of a cell, these guesstimated pin or terminal locations unlikely to be optimal for connecting with the pins or ports of the devices within the cell. Either way, multiple iterations may be required for even a single cell. In addition, even if the circuit designer knows how these pins are connected to each other, the circuit designer may only align or offset these pins by manipulating the cell. In the event that a designer groups a set of components or cells and intends to create a logical cell for the set, the pins of the logical cell or their identifications thereof (e.g., names of the pins) have to be manually created. The designer will then have to find the corresponding pin identifications in the schematic design and associated these manually created identifications with the corresponding pin identifications.
Bottom-up approaches begin with the design of discrete circuit components and proceed to higher hierarchies as the designs of lower hierarchies are complete until the design for the top or highest hierarchy is complete. In these bottom-up approaches, pins and their identifications as well as locations are determined at lower hierarchies in their respective cells. At the higher hierarchies, these pins often present a challenge to routing these pins of an actual or virtual cell because these pins are determined individually for each cell and independent of each other and may thus cause misalignment of pins or terminals at higher hierarchies where these cells are assembled and supposed to be interconnected. To rectify these problems such as pin or terminal misalignment at higher hierarchies, the design process must return to the lower hierarchies where the devices with the misaligned pins are placed, adjust the placement of the devices, and determine whether the pins or terminals are aligned at the next higher hierarchy. These conventional approaches must then proceed to the next higher hierarchy to determine whether there exist other misalignment problems. These conventional approaches may thus iterate multiple times until an acceptable or desirable solution is found. Therefore, there is a need for a better approach to manipulate the hierarchies of an electronic design to effectively and efficiently create a cell for a group of devices.
The problem is exacerbated during the prototyping, floorplanning, placement stage or during the implementation of a portion of an electronic design where no existing IP cells or blocks are available. For example, a designer may be implementing a portion of the design corresponding to a new design for which no existing cells or blocks are available. As another example, a designer may then need to lay out this portion by placing individual components. The design may then need to create one or more cells or blocks for these newly inserted layout components either because of a design requirement or because of a desire or need for reducing the complexity in the appearance of the layout. In these embodiments, the designer may first place a plurality of layout components in a layout and attempt to create one or more cells for the plurality of layout components.
Moreover, many of these layout components may need to be moved or modified to fit various design requirements during these stages. Some conventional approaches group the selected layout components into a cell but do not add any connectivity to such a cell. For example, a cell created by these conventional approaches may have no ports, pins, or terminals to connect to the remaining portion of the electronic design to which this newly created cell belongs. Some conventional approaches attempt to rectify this shortcoming by requiring manual creation of the boundary as well as manual determination of various connections (e.g., pins, terminals, ports, etc.) along the manually created boundary. These conventional approaches invariably involve some guesstimates and hence a number of iterations to finally create the cell with usable connections along the boundary of the cell.
Modern electronic designs may allow only a fixed number wire widths. For example, modern electronic designs may include only wires of the following width values—32-nm, 34-nm, 38-nm, 40-nm, 46-nm, 58-nm, 62-nm, 70-nm, 76-nm, 78-nm, and 80-nm. Moreover, the arrangements of wires are also limited by additional design rules imposed by foundries. For example, foundries may require that a 32-nm wire may only be located immediately adjacent to wires of width values smaller than or equal to 46-nm. That is, a 32-nm wire may not be located immediately adjacent to wires having width values of 58-nm, 62-nm, 70-nm, 76-nm, 78-nm, and 80-nm. Such rules impose perplexing complexities in physical implementations (e.g., floorplanning, placement, routing, etc.) of electronic designs. To further exacerbate the complexities, modern electronic designs may permit only a certain number of device patterns. For example, modern electronic designs may permit a first legal device pattern of PMOS-NMOS-NMOS-PMOS and a second legal device pattern of NMOS-PMOS-PMOS-NMOS in the orientation orthogonal to the direction in which the placement rows lie, but not other combinations such as PMOS-PMOS-NMOS-NMOS, NMOS-NMOS-PMOS-PMOS, etc. where PMOS denotes a p-type metal-oxide-semiconductor transistor, and NMOS denotes a n-type metal-oxide-semiconductor transistor. These complexities may cause further issues when an electronic design is partitioned into smaller portions, each of which is then handed off to different designers or design teams for implementation.
To address some of the aforementioned issues, some conventional approaches use brute force techniques that often require time-consuming and resource-wasting iterative techniques to gradually weed out the inconsistencies in routing track assignments and illegal device patterns.
Therefore, there exists a need for methods, systems, and computer program products for implementing legal routing tracks across virtual hierarchies and legal placement patterns.